The present invention relates to a method for performing a data transaction between a memory device and a master device, and a memory device therefor.
FIG. 1 shows a schematic block diagram of a conventional system 100 for transferring data between a memory subsystem 102 and a plurality of masters 104 via a bus 106. The memory subsystem 102 can be any memory chip or a sub-block within a SoC, which stores information in units of memory banks 108. Each memory bank 108 includes an even cut 110 that stores bytes in the form of a word aligned with even addresses, and an odd cut 112 that stores bytes in the form of a word aligned with odd addresses. The memory subsystem 102 includes a memory controller for performing data transactions between the masters 104 and the memory banks 108.
In a conventional multi-master, multi-bank memory controller architecture, a memory access request from one master 104 is routed to one of the memory banks 108 irrespective of memory width alignment. For example, in a narrow write transaction between a master 104 and a memory bank 108 where a transaction width is less than a width of the bus 106, a strobe signal is provided to mask unused data bits in the bus 106, while in a read transaction between the master 104 and the memory bank 108, the memory bank 108 is accessed fully based on width of the bus 106. The transaction width is determined based on a width of the transferred data.
FIG. 2 is a flow chart of a conventional method 200 for transferring data between the master 104 and the memory bank 108 of the memory subsystem 102 of FIG. 1. Starting at step 202, the memory controller 114 waits for a transaction request sent from the master 104. At step 204, upon receipt of the transaction request at an I/O interface of the memory controller 114, the memory controller 114 identifies if the transaction is a read transaction or a write transaction.
For a read transaction, at step 206, both the even and odd cuts 110 and 112 of the memory bank 108 are enabled. At step 208, the memory controller 114 reads data from both the even and odd cuts 110 and 112 together with an error correction code (ECC). At step 210, the memory controller 114 detects and corrects any ECC errors on both the even and odd cuts. Finally, at step 212, the memory controller 114 sends out corrected data and a response to the I/O interface of the memory controller 114.
On the other hand, for a write transaction request, at step 214, the memory controller 114 identifies if the write transaction is a narrow type write transaction. At step 216, for a narrow type write transaction, the memory controller 114 holds the write transaction for both the even and odd cuts 110 and 112. At step 218, the memory controller 114 initiates a read transaction for the two cuts 110 and 112, and at step 220, data read from the even and odd cuts 110 and 112 is merged with data being held for the write transaction. For a non-narrow type write transaction, step 222 is performed directly after step 214, where the ECC for the even and odd cuts 110 and 112 is calculated. For the narrow type write transaction, the ECC is calculated based on the merged data, while for the non-narrow type write transaction, the ECC is calculated based only on the data to be written to the memory bank 108. At step 224, the memory controller 114 enables both the even and odd cuts 110 and 112. At step 226, the data and ECC are written to both the even and odd cuts 110 and 112, where for the narrow type write transaction, the memory controller 114 writes the merged data and the ECC to the even and odd cuts 110 and 112, while for the non-narrow type write transaction, the memory controller 114 writes the data to be written to the memory bank 108 as well as the ECC to the even and odd cuts 110 and 112. Finally, at step 228, a response is sent to the I/O interface of the memory controller 114.
FIG. 3 is a conventional state machine 300 of a write transaction performed by the memory controller 114. Initially the memory controller 114 is in an idle state 302 via transition 304 if no valid write transaction request is received. Upon receipt of a write transaction request, (i) if only a write address in a memory bank 108 is valid, the memory controller 114 moves to an acknowledge state (W_ACK) 306 via transition 308 to acknowledge the receipt of the write address and wait for write data, (ii) if both the write address and write data are valid, and the transaction length is more than one, the memory controller 114 moves to a first memory access state (W_CS) 310 via transition 312 to access the memory bank 108 and write the write data of a non-last write transaction of the ongoing transaction, or (iii) if both the write address and write data are valid, but the transaction length is one, the memory controller 114 moves to a second memory access state (W_CSL) 314 via transition 316 to access the memory bank 108 and write the write data of a last write transaction clock cycle of the ongoing transaction.
In the W_ACK state 306, the memory controller 114 (i) remains in the W_ACK state 306 via transition 318 if the write data is not valid, (ii) moves to the W_CS state 310 via transition 320 if the write data for the first but not the last write transaction of the ongoing transaction is valid, or (iii) moves to the W_CSL state 314 via transition 322 if the write data for the last write transaction of the ongoing transaction is valid.
In the W_CS state 310, the memory controller 114 (i) remains in the W_CS state 310 via transition 324 until the last write transaction of the ongoing transaction, or (ii) moves to the W_CSL state 314 via transition 326 in the last write transaction of the ongoing transaction.
In the W_CSL state 314, the memory controller 114 (i) remains in the W_CSL state 314 via transition 328 if a new write transaction request together with the write address and write data are valid, and the transaction length is one, (ii) moves to the W_CS state 310 from the W_CSL state 314 via transition 330 if the new write transaction request together with the write address and write data are valid, and the transaction length is more than one, (iii) moves back to the W_ACK state 306 via transition 332 to wait for the write data if only the new write transaction request and the write address are valid, or (iv) moves back to the IDLE state 302 from the W_CSL state 314 via transition 334 if there is no new valid write transaction request.
As can be seen from the flow chart of the conventional method 200 and the state machine 300, both the even and odd cuts 110 and 112 of the memory bank 108 are enabled regardless of the transaction type, and the memory subsystem 102 remains in a single power-on mode in the write transaction regardless of the validity of the write data, which results in high dynamic and leakage power consumption. It is therefore desirable to find a method for reducing power consumption by the memory.